Search - ram verilog

[Other] allidt_20020616.tar

Description: idt的双口ram的读写接口程序，verilog 代码，并且有测试文档-Employing a dual-port ram reader interface program, Verilog code, and a test document
Platform: | Size: 44740 | Author: buttern | Hits:

Description: FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.
Platform: | Size: 16232 | Author: 田世坤 | Hits:

[Other resource] ReadHexFile

Description: 将16进制文件转换成RAM可读的文件,verilog语言编写-229 to 16 documents into RAM readable document, verilog language
Platform: | Size: 521 | Author: 彭琦 | Hits:

[Other resource] altera_ram

Description: 本程序对如何使用altera系列芯片片上ram进行实例演示，采用Verilog HDL语言编写，并使用modelsim与quartus联合进行功能仿真。本原码是红色逻辑开发板的试验程序，值得一看。
Platform: | Size: 180374 | Author: panyouyu | Hits:

[Other resource] dul_ram(yk)

Description: 关于双口RAM的Verilog HDL源码
Platform: | Size: 3091 | Author: 123 | Hits:

[Other resource] verilog_YUYAN

Description: verilog语言写的同步双端口设计文件!!!是一个不错的双口RAM的设计文件！
Platform: | Size: 50259 | Author: JP | Hits:

[Software Engineering] the_ram_of_fPga

Description: 基于FPGA的SDRM设计，VERILOG语言写的同步双端口设计文件!!!是一个不错的双口RAM的设计文件！
Platform: | Size: 8804 | Author: JP | Hits:

[Other resource] an_dcfifo_top_restored

Description: alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输，值得学习。
Platform: | Size: 928622 | Author: alison | Hits:

[VHDL-FPGA-Verilog] zbt_verilog_xilinx

Description: ZBT SRAM控制器参考设计，ZBT SRAM是一种高速同步SRAM）-ZBT SRAM controller reference design, ZBT SRAM is a high-speed synchronous SRAM)
Platform: | Size: 7168 | Author: shang808 | Hits:

[VHDL-FPGA-Verilog] Synthesizable_FIFO_verilog

Description: Synthesizable FIFO Model This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO depth is 4 and the FIFO width is 32 bits.
Platform: | Size: 16384 | Author: lianlianmao | Hits:

[VHDL-FPGA-Verilog] SDR_SDRAM_controler_verilog

Description: 可以用的通用SDRAM控制器,可以用在FPGA上,是SDR类型的-Can use the generic SDRAM controller can be used in the FPGA, the SDR is the type of
Platform: | Size: 9216 | Author: 郑宏超 | Hits:

[VHDL-FPGA-Verilog] InvMod_test

Description: verilog实现的1024位的大数模逆算法，引入RAM作为数据通道-verilog to achieve the 1024 Modular inverse algorithms, the introduction of RAM as a data channel
Platform: | Size: 5120 | Author: 李丹 | Hits:

[VHDL-FPGA-Verilog] DW8051_ALL

Description: 包中包括, DW8051完整的Verilog HDL代码两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!
Platform: | Size: 1588224 | Author: myfingerhurt | Hits:

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[Other] allidt_20020616.tar

[Other resource] DDS_Power

[Other resource] ReadHexFile

[Other resource] altera_ram

[Other resource] dul_ram(yk)

[Other resource] verilog_YUYAN

[Software Engineering] the_ram_of_fPga

[Other resource] an_dcfifo_top_restored

[VHDL-FPGA-Verilog] zbt_verilog_xilinx

[VHDL-FPGA-Verilog] Synthesizable_FIFO_verilog

[VHDL-FPGA-Verilog] SDR_SDRAM_controler_verilog

[VHDL-FPGA-Verilog] InvMod_test

[VHDL-FPGA-Verilog] DW8051_ALL

[VHDL-FPGA-Verilog] fifo_test

[VHDL-FPGA-Verilog] in_out_put

[VHDL-FPGA-Verilog] 61EDA_H182

[Embeded-SCM Develop] ramtest

[VHDL-FPGA-Verilog] 256fft

[VHDL-FPGA-Verilog] DualPortRAM

[VHDL-FPGA-Verilog] dp_ram

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